1. Field of the Invention
This invention relates to a semiconductor integrated circuit device having a booster circuit, and more particularly to a semiconductor integrated circuit in which an externally supplied high voltage is controlled according to a voltage output from a booster circuit.
2. Description of the Related Art
In nonvolatile semiconductor memory devices, or EPROMs having double gate type nonvolatile memory elements of floating gate structure as memory cells, data can be re-programmed, and therefore they are used in various data processing systems such as microcomputer systems. As is well known in the art, the double gate type nonvolatile memory element has two gate electrodes, that is, a floating gate and a control gate. If electrons are injected into the floating gate, the threshold voltage of the memory element is enhanced and therefore it will not be turned on even when a high level voltage, for example, 5 V is applied to the control gate. In contrast, if no electrons are injected into the floating gate, the memory element is kept in a neutral condition and the threshold voltage thereof is kept at the original low voltage level. Therefore, when a high level voltage is applied to the control gate, the memory element is turned on. Thus, data can be stored by the change of the threshold voltage. In reading the data, a high level voltage, for example 5 V, is applied to the control gate. The data stored in the memory element can be detected (read out) through a change in the channel current of the memory element. Further, data can be programmed by applying a voltage of, for example, 12.5 V which is sufficiently higher than the power source voltage (5 V) to the control gate and drain. When such a high voltage is applied, impact ionization occurs in the channel region near the drain, causing electron-hole pairs. At this time, electrons of the electron-hole pairs are injected into the floating gate. The electrons once injected into the floating gate are kept inside the floating gate unless the erasing operation is effected. That is, the memory data can be stored in a nonvolatile fashion.
When such EPROM is in a read mode, a read voltage, for example, 5 V, is applied to the control gate of the memory element, while when in a program mode, a program voltage of 12.5 V, is applied to the control gate and drain of the memory element. Therefore, EPROM has two power source terminals. The first power source terminal continuously receives an external power source voltage 5 V, and a second power source terminal receives a power source voltage of 5 V when in a read mode, but one of 12.5 V when in a program mode.
The EPROM includes a circuit for only data-reading operation, such as a second amplifier, a data output buffer, or the like, and a circuit designed for both data-reading operation and programming operation, such as a column decoder, a row decoder, or the like.
FIG. 1 is a circuit diagram schematically showing the construction of an ordinary EPROM having the nonvolatile memory elements described above as memory cells. Row lines WL1 to WLm are connected to receive decoded outputs from row decoder 131, and column selection lines COL1 to COLn are connected to receive decoded outputs from column decoder 132. The gate of n column selection transistors C1 to Cn are respectively connected to n column selection lines COL1 to COLn, and column selection transistors C1 to Cn are controlled by respective signals supplied via column selection lines COL1 to COLn. First ends of the current paths of column selection transistors C1 to Cn are connected commonly to node 133, and second ends of the current paths are connected to n column lines BL1 to BLn which are arranged to cross row lines WL1 to WLm. Further, memory cells M11 to Mmn constituted by double gate MOS transistors each having a floating gate and a control gate are connected are respective points at which row lines WL1 to WLm cross column lines BL1 to BLn. Each of the control gates of memory cells M11 to Mmn is connected to a corresponding one of row lines WL1 to WLm, each of the drains thereof is connected to a corresponding one of column lines BL1 to BLn, and all the sources thereof are connected to a preset voltage application point, for example, ground voltage (0 V) terminal VS. Node 133 is connected to a source of MOS transistor 134. The drain of MOS transistor 134 is connected to external programming voltage terminal VP, and the gate thereof is connected to an output node of data programming circuit 135. Data programming circuit 135 supplies programming data DIN which is set at a VS voltage or a high voltage according to data of "1" or "0" to be programmed. Further, node 133 is connected to sense amplifier circuit 136, and data corresponding to a potential at node 133 is sensed by means of sense amplifier circuit 136 in the data readout mode.
In the EPROM described above, when data of "0" of programmed into a single memory cell, for example, memory cell M11, signal DIN supplied from data programming circuit 135 is set to a high voltage level and column selection line COL1 is set to a high voltage by a decoded output from column decoder 132. High voltage signal DIN causes transistors 134 to be turned on, and column selection transistor C1 is turned on by column selection line COL1 which is set at a high voltage, causing external programming voltage VP to be applied to column line BL1. At this time, row line WL1 is set to a high voltage by a decoded output from row decoder 131, and thus the control gate and drain of selected memory cell M11 are both set to a high voltage. In this way, electrons generated by impact ionization as described before are injected into the floating gate of memory cell M11, thus programming data "0". In contrast, when data "1" is programmed into memory cell M11, signal DIN from data programming circuit 135 is set to voltage VS of 0 V. At this time, since transistor 134 is kept in the OFF state, external programming voltage VP is not applied to column line BL1. Therefore, the floating gate of selected memory cell M11 is kept in the neutral condition.
Recently, in order to attain high integration density, the size of the nonvolatile memory element described above tends to be reduced, and external programming voltage VP is lowered with the miniaturization. Therefore, it is a common practice to effect data programming in the avalanche region in which the programming efficiency is high in order to attain short programming time and sufficiently large operation margin.
FIG. 2 shows the programming characteristics (drain voltage VD-drain current ID characteristics) of memory cell M11 when a high voltage is applied to the gates of MOS transistors 134 and C1 to Cn and a programming high voltage is applied to the control gate of memory cell M11 in the EPROM of FIG. 1. Curve La in FIG. 2 indicates the dependency of the drain voltage on the drain current of memory cell M11, and line Ld indicates the load characteristics of a load circuit including MOS transistors 134 and C1 operated in the condition described above. At this time, data programming is effected with the drain voltage and the drain current obtained at point PA at which curve La crosses line Ld. Generally, it is well known in the art that the channel length of memory cell M11 varies in a certain range in the manufacturing process. The dependency of the drain voltage on the drain current of memory cell M11 will be indicated by curve Lb or Lc when the channel length becomes longer or shorter than a preset value, respectively. The operation point of data programming is set on point PB at which curve Lb crosses line Ld when the channel length becomes longer. Therefore, in this case, it becomes difficult to effect the data programming in the avalanche region, lowering the programming margin. In contrast, when the channel length becomes shorter, the operation point of data programming is set on point PC at which curve Lc crosses line Ld. In this case, data can be programmed in the avalanche region, but the drain current will significantly increases. Therefore, in order to effect stable programming and keep the drain current at a constant level even when the channel length of the memory cell varies, it becomes necessary to set the operation point of data programming in a limited range. For this purpose, the inclination of the load characteristic curve may be set small as shown by line Le, for example. Therefore, it becomes common practice to apply a high voltage which is stepped up to be higher than external programming voltage VP to the gates of MOS transistors 134 and C1 to Cn, thereby compensating for the voltage drop due to the threshold voltage of each transistor.
The conventional EPROM is generally formed of N-channel structure using an N-channel MOS process. However, in the personal computer such as hand-held computers (lap-top computers), the EPROM tends to be formed of CMOS structure in order to lower the power consumption. For example, column decoder 132, row decoder 131 and data programming circuit 135 in the conventional EPROM shown in FIG. 1 and using a booster circuit are formed of CMOS structure.
However, in the EPROM having such circuits as the column decoder, row decoder and data programming circuit of the CMOS structure which control a high voltage supplied externally by use of the boosted voltage, a latch-up phenomenon tends to easily occur because a high voltage is used for data programming. The latch-up phenomenon will occur when a parasitic thyristor is formed of, for example, a parasitic NPN transistor which is constituted by an N-channel MOS transistor formed in a P-type substrate and a parasitic PNP transistor which is constituted by a P-channel transistor formed in N-type well region, and if the parasitic thyristor is triggered and turned on by a high voltage, thereby causing a D.C. current to flow between the power source terminals. Furthermore it is necessary to use transistors with high drain breakdown voltage as transistors in the high voltage-operated circuit. The transistor with high drain breakdown voltage is formed as shown in the cross section of FIG. 3 in a case of P-channel transistor, for example. That is, source region 172 and drain region 173 of P-type high impurity concentration are formed in N-well region 171, and gate electrode 175 is formed on channel 174 between regions 172 and 173 with an insulation film (not shown) disposed between channel 174 and electrode 175. In order to achieve high drain breakdown voltage, P.sup.- region 176 of low impurity concentration is formed on that portion of drain region 173 which is in contact with channel 174. The structure is known as an LDD (Lightly Doped Drain) structure. As described above, in the LDD structure, since P.sup.- region 176 of low impurity concentration is formed, it is necessary to provide a larger element area in comparison with the ordinary transistor which is not an LDD structure. Further, in a case where a P-channel MOS transistor is formed with a P-type substrate, the P-channel MOS transistor is formed in an N-well region. It becomes necessary to dispose the N-well region in which a circuit for only data reading operation is formed separately from the N-well region in which a circuit for both data-reading operation and programming operation formed.
As described above, in the prior art, P- and N-channel MOS transistors are formed to have high drain breakdown voltage, thus increasing the entire surface area and increasing the chip size. And a latch up phenomenon tends to easily occur because a high voltage is applied to a P-channel MOS transistor and a N-well region.